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NBSG16M 2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer
The NBSG16M is a differential current mode logic (CML) receiver/driver/translator buffer. The device is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities. Inputs incorporate internal 50 W termination resistors and accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The CML output structure contains internal 50 W source termination resistor to VCC. The device generates 400 mV output amplitude with 50 W receiver resistor to VCC. The VBB pin is internally generated voltage supply available to this device only. For all single-ended input conditions, the unused complementary differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open.
http://onsemi.com MARKING DIAGRAM*
QFN-16 MN SUFFIX CASE 485G A L Y W SG 16M ALYW
= Assembly Location = Wafer Lot = Year = Work Week
*For additional marking information, refer to Application Note AND8002/D.
* Maximum Input Clock Frequency > 10 GHz Typical * * * * * *
Maximum Input Data Rate > 10 Gb/s Typical 120 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Negative CML Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V CML Output Level; 400 mV Peak-to-Peak Output with 50 W Receiver Resistor to VCC 50 W Internal Input and Output Termination Resistors and SG Devices
ORDERING INFORMATION
Device NBSG16MMN NBSG16MMNR2 Package 3x3 mm QFN-16 3x3 mm QFN-16 Shipping 123 Units / Rail 3000/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
* * Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL * VBB Reference Voltage Output
(c) Semiconductor Components Industries, LLC, 2004
1
April, 2004 - Rev. 3
Publication Order Number: NBSG16M/D
NBSG16M
VCC VBB 16 VTD D D VTD 15 VEE 14 VEE 13 Exposed Pad (EP)
1 2 NBSG16M 3 4
12 11 10 9
VCC Q Q VCC
5 VCC
6 NC
7 VEE
8 VEE
Figure 1. QFN-16 Pinout (Top View)
Table 1. PIN DESCRIPTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - VTD D D -
LVDS, CML, ECL, LVTTL, LVCMOS Input LVDS, CML, ECL, LVTTL, LVCMOS Input - - - - - - CML Output CML Output - - - - - -
VTD VCC NC VEE VEE VCC Q Q VCC VEE VEE VBB VCC EP
1. The NC pins are electrically connected to the die and MUST be left open. 2. CML outputs require 50 W receiver termination resistor to VCC for proper operation. 3. In the differential configuration when the input termination pin (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation.
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Internal 50 W Termination Pin. See Table 2. (Note 3) Inverted Differential Input (Note 3) Noninverted Differential Input. (Note 3) Internal 50 W Termination Pin. See Table 2. (Note 3) Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. No Connect (Note 1) Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. Noninverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2) Inverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2) Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. Internally Generated ECL Reference Output Voltage Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat-sinking conduit.
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Pin
Name
I/O
Description
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VCC VCC
VTD 50 W D D 50 W VTD VBB 16 mA VEE VEE 50 W 50 W Q Q 50 W 50 W Q Q
Figure 2. Logic Diagram
Figure 3. CML Output Structure
Table 2. Interfacing Options
INTERFACING OPTIONS CML LVDS AC-COUPLED RSECL, PECL, NECL LVTTL, LVCMOS CONNECTIONS Connect VTD and VTD to VCC Connect VTD and VTD together Bias VTD and VTD Inputs within (VIHCMR) Common Mode Range Standard ECL Termination Techniques An external voltage should be applied to the unused complimentary differential input. Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics ESD Protection Human Body Model Machine Model Charged Device Model Value > 1 kV > 100 V > 4 kV Level 1 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 145
Moisture Sensitivity (Note 4) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
4. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI VINPP IIN Iout IBB TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage |D - D| Input Current Through RT (50 W Resistor) Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 5) Thermal Resistance (Junction-to-Case) Wave Solder 0 lfpm 500 lfpm 1S2P (Note 5) < 15 sec. QFN-16 QFN-16 QFN-16 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC - VEE w 2.8 V VCC - VEE < 2.8 V Static Surge Continuous Surge VI v VCC VI w VEE Condition 2 Rating 3.6 -3.6 3.6 -3.6 2.8 |VCC - VEE| 45 80 25 50 1.0 -40 to +85 -65 to +150 42 35 4.0 225 Unit s V V V V V mA mA mA mA mA C C C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 5. JEDEC standard multilayer board - 1S2P (1 signal, 2 power)
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Table 5. DC CHARACTERISTICS, POSITIVE CML OUTPUT VCC = 2.5 V; VEE = 0 V (Note 6)
-40C Symbol ICC VOH VOL VIH VIL VBB VIHCMR Characteristic Positive Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) (Note 8) Input LOW Voltage (Single-Ended) (Note 8) ECL Reference Voltage Output Input HIGH Voltage Common Mode Range (Note 8) (Differential Configuration) Internal Input Termination Resistor Internal Output Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) VEE + 1.275 VEE 1075 1.2 Min 37 VCC - 40 Typ 43 VCC - 10 VCC - 400 VCC - 1.0* VCC - 1.4* 1170 Max 51 VCC VCC- 330 VCC VIH- 0.150 1265 2.5 VEE + 1.275 VEE 1075 1.2 Min 37 VCC - 40 25C Typ 43 VCC - 10 VCC - 400 VCC - 1.0* VCC - 1.4* 1170 Max 51 VCC VCC- 330 VCC VIH- 0.150 1265 2.5 VEE+ 1..275 VEE 1075 1.2 Min 37 VCC - 40 85C Typ 43 VCC - 10 VCC - 400 VCC - 1.0* VCC - 1.4* 1170 Max 51 VCC VCC- 330 VCC VIH- 0.150 1265 2.5 Unit mA mV mV V V mV V
RTIN RTOUT IIH IIL
45 45
50 50 60 25
55 55 100 50
45 45
50 50 60 25
55 55 100 50
45 45
50 50 60 25
55 55 100 50
W W mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -0.965 V. 7. All loading with 50 W to VCC. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. *Typicals used for testing purposes.
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Table 6. DC CHARACTERISTICS, POSITIVE CML OUTPUT VCC = 3.3 V; VEE = 0 V (Note 9)
-40C Symbol ICC VOH VOL VIH VIL VBB VIHCMR Characteristic Positive Power Supply Current Output HIGH Voltage (Note 10) Output LOW Voltage (Note 9) Input HIGH Voltage (Single-Ended) (Note 11) Input LOW Voltage (Single-Ended) (Note 11) ECL Reference Voltage Output Input HIGH Voltage Common Mode Range (Note 11) (Differential Configuration) Internal Input Termination Resistor Internal Output Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) VEE + 1.275 VEE 1875 1.2 Min 37 VCC - 40 Typ 43 VCC - 10 VCC - 400 VCC - 1.0* VCC - 1.4* 1970 Max 51 VCC VCC - 330 VCC VIH - 0.150 2065 3.3 VEE + 1.275 VEE 1875 1.2 Min 37 VCC - 40 25C Typ 43 VCC - 10 VCC - 400 VCC - 1.0* VCC - 1.4* 1970 Max 51 VCC VCC - 330 VCC VIH - 0.150 2065 3.3 VEE + 1.275 VEE 1875 1.2 Min 37 VCC - 40 85C Typ 43 VCC - 10 VCC - 400 VCC - 1.0* VCC - 1.4* 1970 Max 51 VCC VCC - 330 VCC VIH - 0.150 2065 3.3 Unit mA mV mV V V mV V
RTIN RTOUT IIH IIL
45 45
50 50 60 25
55 55 100 50
45 45
50 50 60 25
55 55 100 50
45 45
50 50 60 25
55 55 100 50
W W mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.165 V. 10. All loading with 50 W to VCC. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. *Typicals used for testing purposes.
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Table 7. DC CHARACTERISTICS, NEGATIVE CML OUTPUT VCC = 0 V; VEE = -3.465 to -2.375 V (Note 12)
-40C Symbol ICC VOH VOL VIH VIL VBB VIHCMR Characteristic Positive Power Supply Current Output HIGH Voltage (Note 13) Output LOW Voltage (Note 12) Input HIGH Voltage (Single-Ended) (Note 13) Input LOW Voltage (Single-Ended) (Note 13) ECL Reference Voltage Output Input HIGH Voltage Common Mode Range (Note 14) (Differential Configuration) Internal Input Termination Resistor Internal Output Termination Resistor Input HIGH Current (@ VIH) Input LOW Current (@ VIL) VEE + 1.275 VEE -1425 Min 37 VCC - 40 Typ 43 VCC - 10 VCC - 400 VCC - 1.0* VCC - 1.4* -1330 Max 51 VCC VCC - 330 VCC VIH- 0.150 -1235 VCC VEE + 1.275 VEE -1425 Min 37 VCC - 40 25C Typ 43 VCC - 10 VCC - 400 VCC - 1.0* VCC - 1.4* -1330 Max 51 VCC VCC - 330 VCC VIH- 0.150 -1235 VCC VEE + 1.275 VEE -1425 Min 37 VCC - 40 85C Typ 43 VCC - 10 VCC - 400 VCC - 1.0* VCC - 1.4* -1330 Max 51 VCC VCC - 330 VCC VIH- 0.150 -1235 VCC Unit mA mV mV V V mV V
VEE+1.2
VEE+1.2
VEE+1.2
RTIN RTOUT IIH IIL
45 45
50 50 60 25
55 55 100 50
45 45
50 50 60 25
55 55 100 50
45 45
50 50 60 25
55 55 100 50
W W mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Input and output parameters vary 1:1 with VCC. 13. All loading with 50 W to VCC. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. *Typicals used for testing purposes.
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Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
-40C Symbol VOUTPP tPLH, tPHL tSKEW tJITTER Characteristic Output Voltage Amplitude (See Figure 4) (Note 15) Propagation Delay to Output Differential Duty Cycle Skew (Note 16) RMS Random Clock Jitter (Note 18) fin < 10 GHz Peak-to-Peak Data Dependent Jitter (Note 19) fin < 10 Gb/s VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 17) Output Rise/Fall Times @ 1 GHz (20% - 80%) Q, Q 75 21 35 0.2 8 1 15 2500 53 75 21 35 0.2 8 1 15 2500 53 75 21 35 0.2 8 1.0 15 2500 53 mV ps fin < 7 GHz fin < 10 GHz Min 300 200 90 Typ 400 250 110 3 150 15 Max Min 300 200 100 25C Typ 400 250 120 3 150 15 Max Min 300 100 100 85C Typ 400 150 125 3 155 15 Max Unit mV ps ps ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 15. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC. Input edge rates 40 ps (20% - 80%). 16. See Figure 5 tskew = |tPLH - tPHL| for a nominal 50% differential clock input waveform. 17. VINPP(max) cannot exceed VCC - VEE. (Applicable only when VCC - VEE < 2500 mV). Input voltage swing is a single-ended measurement operating in differential mode. 18. Additive RMS jitter with 50% duty cycle clock signal at 10GHz. 19. Additive Peak-to-Peak data dependent jitter with NRZ PRBS231-1 data rate at 10 Gb/s.
500 OUTPUT VOLTAGE AMPLITUDE (mV) 450 400 350 300 250 200 150 100 50 0 0 1 2 3 4 5 6 FREQUENCY (GHz) 7 8 9 10 VCC - VEE = 2.5 V VCC - VEE = 3.3 V
Figure 4. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) at Ambient Temperature (Typical)
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D D Q Q tPLH
VINPP(D) = VIH(D) - DIL(D) VINPP(D) = VIH(D) - DIL(D)
VOUTPP(Q) = VOH(Q) - VOL(Q) VOUTPP(Q) = VOH(Q) - VOL(Q) tPHL
Figure 5. AC Reference Measurement
VCC
Zo = 50 W Q Driver Device Q Zo = 50 W
50 W
50 W D Receiver Device D
Figure 6. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices)
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Application Information
All inputs can accept PECL, CML, and LVDS signal levels. The input voltage can range from VCC to 1.2 V.
VCC
Examples interfaces are illustrated below in a 50 W environment (Z = 50 W).
VCC
50 W
50 W SG16M
Q Z VCC Z Q VCC
D VTD 50 W SG16M
D VTD
50 W
VEE
VEE
Figure 7. CML to CML Interface
VCC
VCC
50 W PECL Driver RT
Z VBias Z
D VTD 50 W SG16M D VBias VTD 50 W
50 W RT
Recommended RT Values VCC RT 5.0 V 290 W 3.3 V 150 W 2.5 V 80 W VEE
VEE VEE
Figure 9. PECL to CML Receiver Interface
VCC
VCC
Z LVDS Driver Z
D VTD 50 W SG16M D VTD 50 W
VEE
VEE
Figure 8. LVDS to CML Receiver Interface
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PACKAGE DIMENSIONS
-X- A M
QFN-16 MN SUFFIX CASE 485G-01 ISSUE A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 3.00 BSC 3.00 BSC 0.80 1.00 0.23 0.28 1.75 1.85 1.75 1.85 0.50 BSC 0.875 0.925 0.20 REF 0.00 0.05 0.35 0.45 1.50 BSC 1.50 BSC 0.875 0.925 0.60 0.80 INCHES MIN MAX 0.118 BSC 0.118 BSC 0.031 0.039 0.009 0.011 0.069 0.073 0.069 0.073 0.020 BSC 0.034 0.036 0.008 REF 0.000 0.002 0.014 0.018 0.059 BSC 0.059 BSC 0.034 0.036 0.024 0.031
-Y-
B N 0.25 (0.010) T 0.25 (0.010) T J R 0.08 (0.003) T E H G
5 8
DIM A B C D E F G H J K L M N P R
C K -T-
SEATING PLANE
L
4
9
F
1 12
16
13
P
D
NOTE 3 M
0.10 (0.004)
TXY
SOLDERING FOOTPRINT
3.25 0.128 0.30 0.012
0.575 0.022
3.25 0.128
1.50 0.059
0.50 0.02
0.30 0.012
SCALE 10:1 mm inches
QFN-16, 3x3 mm, EP 2x2 mm
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